Miniaturization of a semiconductor integrated circuit has been advanced according to scaling rules, and a wiring has been miniaturized along with elements of MOS transistors etc. A copper wiring with lower resistance has become a mainstream replacing an aluminum wiring. Patterning copper wiring with high accuracy is difficult. Thus, a damascene wiring is employed in which a recessed portion is formed in an insulating film to bury a wiring. Copper diffusion in an insulating film deteriorates insulating characteristics. Hence, a configuration is employed in which a copper wiring is wrapped, for example, by a barrier metal film or an insulating copper diffusion preventing film. In many cases, a copper wiring layer is formed by plating. A recessed portion for a wiring is formed over an interlayer dielectric film and a barrier metal film, a plating seed layer is formed by sputtering, and a copper layer is formed over the seed layer by electrolytic plating. The barrier metal film has a function to barrier against diffusion of copper atoms from the copper layer, and is formed, for example, with TiN, Ta, Ta/TaN or Ti. The seed layer functions as an electrode for electrolytic plating and as a seed for plating film formation, and formed with copper or a copper alloy. The barrier metal film and the seed layer formed by sputtering are formed over the interlayer dielectric film as well. The plating layer is formed over the seed layer. Unnecessary metal layers over the interlayer dielectric film are removed by chemical mechanical polishing (CMP) and a SiC or SiN insulating copper diffusion preventing film is deposited so as to cover the copper wiring and the interlayer dielectric film. In this manner, sides and a lower surface of the copper wiring formed as described above are covered by the seed layer and the barrier metal film, and the upper surface is covered by an insulating copper diffusion preventing film.
A melting point of copper is higher than that of aluminum. Thus, copper is an element in which migration is difficult to occur. However, electro migration (EM) may not be ignored in minute wirings (thin width wiring, narrow width wiring). Stress migration (SM) occurs in a large-width wiring (wide wiring). Suppressing migration, for example, by adding another element to copper to make a copper alloy has been studied.
According to Japanese Laid-open Patent No. H10-209156, when Cu—Ta, to which Ta of 0.5 wt. % is added, is heat-treated in an H reductive atmosphere, Ta is precipitated at the Cu grain boundary and suppresses the grain boundary diffusion. Accordingly, a void is hardly created, and the EM resistance is enhanced.
According to WO 2004/53971, an example is introduced in which a countermeasure for EM resistance and SM resistance is applied. In the example, additional elements in the copper alloy seed layer is diffused into a copper layer by heat treatment to form a copper alloy after forming a copper wiring film by using a copper alloy (Cu—Sn etc.) seed layer. When a copper alloy seed layer in which the additional elements that remain in crystal grains increases resistivity of a copper alloy wiring is formed by sputtering, the copper alloy seed layer deposited at a bottom of the wiring trench becomes thinner in a thin-width wiring compared with that in a large-width wiring. As a result, resistivity of the Cu wiring becomes low and resistivity of the Cu wirings varies depending on the wiring width. According to the embodiment, a method to suppress Cu migration is proposed. In the method, for example, additional elements such as Ti, Zn, Hf, Cr, Co, Al, Sn, Ni, Mg, and Ag are diffused from above the copper wiring film into the copper layer to Cu grain boundary and the vicinity that become SM and EM diffusion routes, thereby suppressing Cu migration. Oxidization of copper may be suppressed when stable metal oxide is formed by the additional elements even if the copper layer is exposed to oxidized species.
According to Japanese Laid-open Patent No. 2006-80234, a Cu alloy seed layer is formed such that the film thickness of sidewall portions and the film thickness of the bottom portions of the wiring trenches for a thin-width wiring and for a large-width wiring are substantially the same. A Cu layer is deposited over the seed layer by electroplating and annealed to form a wiring in which a ratio of an additional element decreases as the wiring trench becomes wider. The seed layer is formed, for example, by sputtering or CVD. However, the disclosure does not describe a specific film formation parameter that allows to control and adjust formation of a seed layer with substantially uniform film thickness. The additional element of the seed layer is assumed to be diffused typically in the copper layer. However, the disclosure does not describe how the additional element of the seed layer may be diffused typically in the copper layer.
In order to suppress a parasitic capacitance of a wiring, the interlayer dielectric film is preferably formed with materials with a low dielectric constant. For example, as a CVD low dielectric constant film, the following materials have been used. The materials include hydrogenated silicon oxycarbide (SiCOH) such as Aurora™ of ASM International NV, Black Diamond™ of Applied Materials, and CORAL™ of Novellus Systems and an organic coating film, SilK™, and a porous material such as porous silica. These materials have properties that easily permeate water content. When water content reaches a barrier metal film, oxidization etc. may be caused, thereby the barrier metal layer may be altered, and the barrier property may be lost.
According to M. Haneda et al., “Self-Restored Barrier using Cu—Mn alloy”, AMC 2007, pp.27-28 and H. Kudo et al., “Further Enhancement of Electro-migration Resistance by Combination of Self-aligned Barrier and Copper Wiring Encapsulation Techniques for 32-nm Nodes and Beyond”, IITC 2008, pp. 117-119, the inventors reported that a dual damascene structure in 45 nm generation is used to fabricate a semiconductor device to which a Cu—Mn alloy seed layer is applied over a Ta barrier metal film, and even when the barrier metal film is thin, the barrier property is self-restored by the additional element Mn of the alloy. Hence, reliability of the copper wiring is improved. According to M. Haneda and H. Kudo, an element mapping in the wiring of the self-restored barrier layer that is formed when heat treatment is applied to a sample of the wiring structure for 30 minutes at 350 degrees Celsius may be referred to.
A self-restored response of the barrier by Mn occurs when heat of 200 to 400 degree Celsius is applied, and heat that is applied in a subsequent manufacturing process, for example, the temperature when forming a cap film by CVD after forming a conductive unit may be utilized. Accordingly, the self-restored barrier layer is easily formed without applying heat separately.
A. Isobayashi et al., “Thermally Robust Cu Interconnects with Cu—Ag Alloy for sub 45 nm Node”, IEEE IEDM 04, 2004, pp.953-956, describes forming a copper layer using a Cu—Ag alloy obtained by doping Ag to Cu which suppresses generation of voids due to stress migration and improves reliability.